The size of a metal-oxide-semiconductor (“MOS”) transistor has been continuously scaled down in the past decades in order to meet performance and density requirements for the transistors. Scaling down of the transistor size reduces area capacitance and increases the speed of the transistor. Various transistor designs or process options are used to improve the transistor performance. For example, use of Silicon-on-Insulator (“SOI”) technology in the transistor fabrication reduces current leakage into the silicon surrounding the transistor. This decreases the power requirements of the transistor and improves performance of the transistor.
One way to improve performance of the transistor is to increase the transistor speed by creating a strained channel. FIG. 1 illustrates a semiconductor transistor structure 200 having a strained channel 201 with increased electron mobility. The strained channel 201 is made of a strained Si layer epitaxially grown on the silicon germanium (“SiGe”) substrate 202. A gate dielectric 203 is placed between a gate electrode 204 and the strained channel 201. A source region 205 and a drain region 206 are on the opposing sides of the gate electrode 204. A lattice constant that denotes the size of the unit cell in a crystal lattice is smaller for Si material than for SiGe material. Such difference in the lattice constants of Si material and SiGe material produces a tensile strain in the Si layer grown on the SiGe substrate. The tensile stress in the Si layer increases the mobility of electrons. The tensile stress, however, does not affect significantly the mobility of holes.
Another technique of forming a stressed transistor channel is described in the U.S. Pat. No. 6,621,131. FIG. 2 shows a semiconductor transistor structure 300 with the SiGe alloy source 40A and drain 40B films epitaxially grown in the recesses etched into a layer of epitaxial Si 10 on opposing sides of the gate electrode 18. Because SiGe has a larger lattice constant than Si, it induces a compressive stress in the layer of epitaxial Si 10 under the gate electrode 18 between the source 40A and drain 40B films, such that a compressively strained transistor channel 30 is formed. The semiconductor transistor structure 300 also includes the gate dielectric 14 placed between the gate electrode 18 and the layer of epitaxial Si 10, and the spacers 26A and 26B along the sidewalls of the gate electrode 18, as shown in FIG. 2. FIG. 2 also shows the field isolation regions 12 that isolate wells of different conductivity types and isolate adjacent transistors. The compressive stress in a transistor channel 30 increases the mobility of holes. To create a tensile stressed transistor channel with increased mobility of electrons, SiC alloy is deposited into the recesses formed in the epitaxial Si layer on opposing sides of the gate electrode. Because SiC has smaller lattice constant than Si, it induces a tensile stress in the Si layer under the gate electrode between the source and drain films, such that a tensile strained transistor channel is created.
The compressively strained transistor channel for holes and tensile strained transistor channel for electrons require the materials that have different lattice constants relative to the lattice constant of the substrate that can result in more processing steps and complicate the transistor manufacturing. In addition, epitaxial growth of the semiconductor materials having different lattice constants on one another can create excess defects on the growth interface.